FIFO Board

From SpaceWeather

Here is the Senior Design Project Report Media:reference_manual.doc

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FIFO Board

Analog Devices -

• HSC-ADC-EVALC includes Xilinx Virtex-4 FPGA Memory Board

Parallel input at 644 MSPS SDR and 800 MSPS DDR

two 18-bit channels of parallel CMOS or LVDS inputs from the ADC

Links

Here are some links relating to the Virtex-4 FPGA and the FIFO

FIFO Specs

http://www.analog.com/static/imported-files/eval_boards/265181843HSC_ADC_EVALC.pdf

FPGA Virtex-4 Packaging and Pinout

http://www.supplyframe.com/partsearchservlet/partnerWormhole.action?id=869550&partnerName=DSA

FPGA Virtex-4 Text Pinout

http://www.xilinx.com/support/packagefiles/v4packages/4vfx12ff668.txt

Spartan3E User Guide

http://www.eece.unm.edu/vhdl/labs2010/spring2010/docs/spartan3e.pdf

ML403 Board Pin Out

http://www.xilinx.com/support/documentation/boards_and_kits/ug080.pdf

UART VHDL Model

http://www.asic-world.com/examples/vhdl/uart.html